Lesson 5 — Intermediate

Computer Arithmetic (ALU, Floating Point)

CPU ki har calculation isi lesson ke concepts se hoti hai — adders se shuru, floating point tak. Is lesson mein hum dekhenge ALU kaise bana hai, ripple carry aur carry look-ahead adder ka farak (speed numericals ke saath), multiplication/division algorithms, aur IEEE 754 float format jo har jagah use hota hai.

⏱ 16 min• Intermediate• Addressing Modes

ALU kya karta hai

WHAT

ALU (Arithmetic Logic Unit) computer ka wo hissa hai jo saari calculations (+, −, ×, ÷) aur comparisons/logic (AND, OR, NOT, >, =) karta hai. Iske andar adders, subtractors, comparators aur shifter circuits hote hain.

WHEN

Har instruction jo kuch compute karti hai — add, compare, address calculate — sab execute stage mein ALU se guzarte hain. Even branch ka condition ALU hi set karta hai.

WHERE

CPU ke andar, Control Unit ke saath. Arithmetic instructions seedhe, baaki (address calc, flag setting) indirectly ALU par chalte hain.

ALU ka dil hai adder — kyunki subtract bhi 2s-complement add se hota hai, multiplication repeated addition hai, division repeated subtraction. Ek achha adder = achha processor.

Adders — half, full, ripple carry, CLA

Half Adder : 2 inputs (A, B)           → Sum, Carry
Full Adder : 3 inputs (A, B, Cin)      → Sum, Cout
  Full adder = 2 half adders + OR gate

n-bit Ripple Carry Adder (RCA) :
  full adders chain mein — har stage ka carry agle ko
  delay = n × t_FA  (carry ko chhup chalna padta hai → SLOW)
  ex: 16-bit RCA delay = 16 × t_FA

Carry Look-Ahead Adder (CLA) — carry PEHLE se calculate :
  Generate  Gi = Ai . Bi
  Propagate Pi = Ai XOR Bi
  Ci+1 = Gi + Pi . Ci
  C1 = G0 + P0.C0
  C2 = G1 + P1.G0 + P1.P0.C0   (parallel — chain nahi)
  → FAST, lekin hardware zyada chahiye (gates zyada)

RCA simple par slow (delay n ke saath badhti hai), CLA fast par hardware-heavy. Real processors mein chunks ke CLA + RCA ka mix use hota hai. Bigger adder delay dekhne wala GATE ka favourite numerical hai.

GATE formula: n-bit RCA ka delay ≈ n × full-adder delay. 8-bit → 8t, 32-bit → 32t. CLA ka delay logarithmic hota hai level of lookahead ke saath — isliye 64-bit machines mein CLA hi use hota hai.

Multiplication aur Division algorithms

UNSIGNED MULTIPLICATION (shift & add) :
  11 × 5  = 1011 × 0101
  partial products (bit = 1 hone pe shift-add) :
    1011          (× 1, shift 0)
  +  0000         (× 0, shift 1)
  + 101100        (× 1, shift 2)  = 44
  +0000000        (× 0, shift 3)
  = 110111 = 55 ✓

SIGNED MULTIPLICATION → BOOTH ALGORITHM :
  runs of 1s ko ek saath handle karta hai (add + subtract)
  -3 × 5 bhi same flow se — sign ka jhanjhat nahi
  extra benefit : consecutive 1s → cycles kam

DIVISION :
  Restoring division     : subtract kiya, negative aaya toh restore
  Non-restoring division : restore nahi, aage sign se decide
  Steps = quotient ke bits nikalte jao (shift-subtract loop)

Multiplication speed: partial products parallel banake add karo (carry-save adder tree) — modern CPUs mein 1 cycle.
Division: multiplication se hamesha slow — isliye 1/x reciprocal approximation + multiply use hota hai.
Booth: GATE mein poochha jaata hai — signed numbers ka standard method, runs of 1s compress karta hai.

IEEE 754 floating point

IEEE 754 SINGLE PRECISION (32 bit) :
| Sign 1 bit | Exponent 8 bit | Mantissa 23 bit |

Sign     : 0 = positive, 1 = negative
Exponent : bias 127 se subtract (stored = actual + 127)
Mantissa : normalized 1.xxxx — leading 1 CHHUP jata hai (implicit)
Value    = (-1)^S × 1.Mantissa × 2^(Exp - 127)

DOUBLE PRECISION (64 bit) : 1 sign + 11 exp (bias 1023) + 52 mantissa

EXAMPLE : -6.75 ko binary mein
  6.75 = 110.11 = 1.1011 × 2^2
  sign = 1, exp = 2 + 127 = 129 = 10000001
  mantissa = 1011000...000 (23 bits)
  → 1 10000001 10110000000000000000000

Ise hi phone, browser aur har language mein float chalta hai. Chhote-chhote rounding errors isi format ke precision se aate hain — mantissa jitna lamba, precision utni zyada.

Exam trap: Single precision bias = 127, double = 1023 — ye do numbers rat lo. Aur exponent mein 255 (all ones) = infinity/NaN reserve hai, isliye bias 127 ke saath max exponent actual 127 + something hota hai. Conversion numerical GATE ka permanent guest hai.

Exercise

Question: IEEE 754 single precision mein exponent ke kitne bits hote hain? Sirf number daalo.

Question: Single precision mein exponent ka bias kya hai? Sirf number daalo.

Question: n-bit ripple carry adder ki delay n × kya hoti hai? (full adder delay / clock cycle)

Common mistakes

Bias ko chhod dena: Exponent = actual exponent + 127 (single). Exam mein bina bias ke answer deta hai option mein — trap hai, hamesha add/subtract karo.
Ripple carry ko fast samajhna: RCA ka delay n ke saath linear badhta hai — carry chain ka wait. CLA isi liye bana (parallel carry).
Half aur full adder ka inputs confusion: Half = 2 inputs (Cin nahi), Full = 3 inputs (Cin hai). Definition question har exam mein aata hai.

Desi example: Dukaan ka float bill

Mobile app dukaan ka bill float mein dikhata hai — ₹6.75. Purane calculator mein wahi dikhega 6.74999... — ye IEEE 754 ka precision khel hai:

6.75 = 1.1011 × 2^2 (binary)
Single: 1 10000001 10110000000000000000000
App = smart rounding, purana calc = mantissa truncate
Rounding error = representation ka natural side effect

Exam mapping (GATE / TCS / UGC)

GATE: IEEE 754 conversion (-6.75 jaisa) — har saal kahin na kahin.
GATE: RCA delay aur CLA generate/propagate equations.
TCS NQT: "IEEE 754 single mein sign/exponent/mantissa bits" — classic.
Trap: "Bias of double precision = 127" — galat, wo 1023 hai.

Lesson complete?

Arithmetic clear — ALU ab tumhare liye black box nahi raha. Agla lesson — Control Unit — mein dekhenge CPU instructions ko signals kaise banata hai (hardwired vs microprogrammed).