Lesson 11 — Intermediate

Instruction Pipelining

Ek instruction ko alag-alag stages mein tod ke saare instructions ko ek saath andar daal do — ye pipelining hai, CPU ki sabse important speedup technique. Is lesson mein hum dekhenge stages kya hain, timing diagram kaise padhte hain, aur speedup/throughput/efficiency ke formulas jo GATE ka dil jeete hain.

Pipelining kya hai

Juice stall wala example socho — ek banda sab karta tha toh ek glass2 minute. Chaar banda laga ke har station ek kaam kare toh har minute ek glass. Ek glass ka time same, output 4× — yahi pipelining hai.

Stages aur timing diagram

CLASSIC 5-STAGE PIPELINE (MIPS jaisa) :
  IF  : Instruction Fetch — memory se instruction padho (PC se)
  ID  : Instruction Decode — samjho kya hai + registers padho
  EX  : Execute — ALU operation / address calculate / branch
  MEM : Memory access — LOAD/STORE ke liye memory read/write
  WB  : Write Back — result register mein likho

TIMING (har column = ek clock cycle) :
       C1   C2   C3   C4   C5   C6   C7
  I1   IF   ID   EX   MEM  WB
  I2        IF   ID   EX   MEM  WB
  I3             IF   ID   EX   MEM  WB
  I4                  IF   ID   EX   MEM  WB

→ C4 ke baad har cycle ek NAYI instruction complete (throughput = 1/cycle)
→ pehla result C5 mein, phir har cycle ek naya result

Diagram padhne ka rule: har instruction left-shifted ek column. Stall ho toh wahan gap daalo (agla lesson mein hazards). Pipeline ka cycle time = slowest stage + register latch overhead — isliye stages ko barabar chhota rakha jaata hai.

Speedup, throughput, efficiency — formulas + numerical

NON-PIPELINED time : T = n × k × t
  n = instructions, k = stages, t = ek stage/cycle time

PIPELINED time : T = (k + n - 1) × t
  pehla instruction k cycles, baaki sabko ek-ek cycle

SPEEDUP = (n × k) / (k + n - 1)
  n → ∞ par Speedup → k   (MAX speedup = number of stages)

THROUGHPUT = n / T_pipeline
EFFICIENCY = Speedup / k   (utilisation of stages)

NUMERICAL : k = 5 stages, t = 2 ns, n = 100 instructions
  Non-pipe = 100 × 5 × 2 = 1000 ns
  Pipe     = (5 + 100 - 1) × 2 = 208 ns
  Speedup  = 1000 / 208 ≈ 4.81  (ideal max = 5)

Perfect linear speedup tabhi jab sab stages EQUAL time lein

Formula ka logic yaad rakho: pipeline mein sirf pehla instruction poora k (stages) leta hai, baaki n−1 instructions ek-ek cycle mein bahar nikalte hain. Isliye (k + n − 1).

Pipeline ke types aur design points

• Instruction pipeline: instructions ke stages alag-alag — ye wahi hum padh rahe hain.
• Arithmetic pipeline: floating point operations (add, multiply) ke chhote steps.
• Unpipelined vs partially pipelined vs fully pipelined: processor generations ka comparison.
• Superpipelining: stages aur chhoti karo, depth zyada — deeper pipeline (15-20 stages aajkal).
• Scalar vs Superscalar: ek instruction/cycle vs ek cycle mein multiple pipelines parallel (dual-issue).

Pipeline depth ka trade-off :
  stages zyada chhoti → clock tez (GHz badhta)
  lekin : branch penalty zyada, hazards zyada, power zyada

  Example : 5-stage (classic, 1 GHz)
            14-20 stage (modern superscalar, 4-5 GHz)

Superscalar : ek cycle mein 2-4 instructions issue
  = do parallel pipelines + dynamic scheduling (OOO execution)

Exercise

Common mistakes

• Pipelining ko latency reduction samajhna: Ek instruction ka time kam nahi hota (5 stages → 5 cycles + overhead). Faida hai throughput — per unit time zyada instructions.
• Speedup formula ulta likhna: T = (k + n − 1) × cycle time, speedup = nk / (k + n − 1). Non-pipelined = n × k × t. Do formulas ke beech swap common galti hai.
• Max speedup ko infinite bolna: Max speedup = k (stages) — wo bhi sirf n bahut zyada ho toh. Infinite kabhi nahi, aur stages unequal hon toh aur kam.

Ek banda : cut → marinate → skewer → grill = 4 min/plate
4 stations : har station ek hi kaam
  har 1 min mein ek plate OUT (throughput 4×)
Ek plate ki latency : phir bhi 4 min (kam nahi hui)
Pipeline = station wise expert + round the clock flow