Lesson 9 — Intermediate

Virtual Memory (Paging & Segmentation)

Memory kam hai, program bada hai — phir bhi chal jaata hai. Ye virtual memory ka jaadu hai. Is lesson mein hum dekhenge paging aur segmentation ka farak, address translation kaise hoti hai (TLB ke saath), page fault kya hai, thrashing kyun hoti hai, aur replacement algorithms par Belady jaisa GATE trap.

⏱ 16 min• Intermediate• Cache Memory

Virtual memory kya hai

WHAT

Virtual memory ka matlab hai — har process ko lagta hai ki uske paas bada-address space hai, jabki physically RAM chhoti hai. Disk ko RAM ki tarah use karke bada program chhote RAM mein chal jaata hai (demand paging).

WHEN

Jab RAM kam pade, jab ek saath bade programs chalein, ya jab process ko isolation chahiye — virtual memory har modern OS mein ON hoti hai.

WHERE

Har laptop/phone/server pe — tumhare phone mein 6GB RAM ho ke bhi 10 apps background mein rehte hain kyunki pages disk pe swap ho sakte hain.

Do lafz samjho: logical address (jo program sochta hai) aur physical address (jo RAM actually hai). Virtual memory in dono ke beech ka translation layer hai — MMU (Memory Management Unit) hardware mein ye kaam karta hai.

Paging

PAGING : logical memory ko fixed-size PAGES mein,
physical memory ko same-size FRAMES mein toda
  → koi external fragmentation nahi (page har jagah fit)

Example : 32-bit logical address, page size = 4 KB (2^12)
  offset bits = log2(4K) = 12
  page number = 32 - 12 = 20 bits
  → page table entries = 2^20 per process (bahut badi!
    isliye multi-level page table use hoti hai)

Address translation :
  logical addr = | Page# | Offset |
  Page# → Page Table → Frame#
  physical addr = | Frame# | Offset |   (offset same rehta hai)

Page table : har process ki apni (OS memory mein rakhti hai)
Page table register (PTBR) : CPU ko pata hai kahan hai

Ek page har jagah fit ho jaata hai — isliye external fragmentation khatam. Lekin page ke andar ka waste (process ka last page adhoora) = internal fragmentation — ye bachta hai.

GATE calculation: Page table size = number of entries × entry size. Example: 32-bit address, 4KB pages, 4-byte entry → 2^20 × 4 = 4 MB per process. Ye number dekh kar hi samajh aata hai ki single-level table kaam nahi karti — multi-level ya hashed table chahiye.

Segmentation

SEGMENTATION : logical memory ko VARIABLE-size segments mein
  code segment, data segment, stack segment — logical units har ek alag

Segment Table : har segment ka (Base, Limit)
  Base = segment kahan shuru physical memory mein
  Limit = size check (overflow = trap — protection!) 

Translation : logical = | Segment# | Offset |
  offset ≥ Limit → fault (protection violation)
  physical = Base + Offset

PAGING vs SEGMENTATION :
  Paging   : fixed size, OS ka kaam, internal frag, transparent
  Segmented: variable size, programmer/compiler ka view,
             protection aasaan, EXTERNAL fragmentation
  Modern : SEGMENTED + PAGING (x86) — dono ke fayde

Paging ka fayda: fragmentation external nahi, management simple.
Segmentation ka fayda: logical protection — code segment read-only, stack growing down.
Combination: segment ke andar pages — x86/64-bit machines isi par chalte hain.

TLB, page fault aur replacement

TLB (Translation Lookaside Buffer) : page table ka CACHE
  har translation ke liye poora page table padhna = 2 memory refs
  TLB hit → seedha frame# (1 reference bachta hai)

EAT = h × (TLB + mem) + (1-h) × (TLB + 2×mem)
  Example h=0.9, TLB=20ns, mem=100ns → 0.9×120 + 0.1×220 = 130 ns

PAGE FAULT : refer ki gayi page RAM mein NAHI (disk pe hai)
  → OS interrupt → page disk se frame mein load → retry

THRASHING : bahut zyada page faults = CPU sirf paging mein laga
  Reason : processes ko kam frames mile (working set poori nahi)

REPLACEMENT ALGORITHMS (kaunsa page nikaalo):
  FIFO   : sabse purana nikalo → BELADY ka anomaly possible!
  LRU    : sabse purana access wala (achha, costly implement)
  Optimal : jo sabse der baad aayega (best, impossible in practice)

Belady : frames badhane se FIFO mein page faults BADH sakte hain
(LRU/Optimal mein nahi — stack property)

Yaad rakho: Page fault ek ERROR nahi — ye normal event hai (page abhi disk pe hai, load karo). Lekin thodi-thodi der mein har jagah fault = thrashing, tab system lagta hai. Difference interview mein zaroor poochha jaata hai.

Exercise

Question: Jab refer ki gayi page RAM mein na mile toh kya trigger hota hai? (page fault / cache miss / hardware trap)

Question: 32-bit logical address aur 4KB page size mein page number ke kitne bits? Sirf number daalo.

Question: FIFO replacement mein frames badhane par page faults ka badh jaana kis anomaly ke naam se jaana jaata hai? (belady / thrashing / lru)

Common mistakes

Page fault ko error samajhna: Page fault normal hai — page disk pe hai, load karo. Error tab hai jab OS handle na kar paye (invalid address).
Logical aur physical address same samajhna: Logical = program ka socha hua, physical = RAM ka actual. Virtual memory isi translation ka naam hai (MMU karta hai).
Belady aur thrashing ko same bolna: Belady = FIFO replacement ka anomaly (frames badhane par faults badhe). Thrashing = memory shortage se bahut zyada faults. Dono alag cheezein hain.

Desi example: Library se chapter mangwana

Tumhari poori library disk jaisi hai, desk chhoti RAM. Demand paging = sirf wahi chapter laao jo abhi padhna hai:

Padhna shuru → chapter desk pe NAHI (page fault)
→ librarian (OS) library (disk) se laayi → desk (frame)
→ ab padho — dobara nahi jaana (cache/TLB hit)
Saare chapters ek saath = desk na chale — thrashing
Desk plan = page table, jaldi wale chapters = TLB

Exam mapping (GATE / UGC / TCS)

GATE: page table size calculation (entries × entry size) — recurring numerical.
GATE: TLB hit ratio se effective access time.
UGC-NET: paging vs segmentation comparison — definition question.
Trap: "Paging causes external fragmentation" — galat, paging mein internal fragmentation hota hai.

Lesson complete?

Virtual memory clear — ab program chhote RAM mein bada lag sakta hai. Agla lesson — System Buses & DMA — mein dekhenge CPU, memory aur I/O ek doosre se kaise baat karte hain.