Lesson 10 — Intermediate

System Buses & DMA

CPU, memory aur I/O ko jodne wali highway hai bus — aur us highway ka fast lane hai DMA. Is lesson mein hum dekhenge bus kitne type ki hoti hain, synchronous/asynchronous kaise chalti hain, arbitration kya hai, aur DMA kaise CPU ke bina data transfer kar leta hai.

⏱ 14 min• Intermediate• Virtual Memory

Bus kya hai

WHAT

Bus ek shared set of electrical lines hai jo CPU, memory aur I/O devices ko aapas mein jodta hai. Teen type ki lines hoti hain — address (kahan), data (kya) aur control (kab/kaise).

WHEN

Har memory access, har I/O transfer, har interrupt — sab bus pe hi hote hain. Ek cycle bhi bina bus ke nahi chalta.

WHERE

Motherboard pe — CPU se memory tak, expansion slots tak (PCIe), aur internal device links tak. Bus width/speed directly performance affect karti hai.

Bus ka fayda shared structure hai — alag-alag wires CPU-se-memory, CPU-se-I/O ke liye na bana ke ek common highway. Cost bachti hai, lekin arbitration chahiye (kaun kab use kare) — wo alag section hai.

Address, data aur control bus + timing

ADDRESS BUS : CPU → memory/I/O (ONE-WAY) — width = kitne addresses
  32-bit → 2^32 = 4 GB, 64-bit → huge

DATA BUS    : DONO taraf (bidirectional) — read mein aata, write mein jaata
  width = ek cycle mein kitna data (8, 16, 32, 64 bit)

CONTROL BUS : Read/Write, interrupt lines, clock, bus request/grant,
              MREQ, IORQ, HOLD/HLDA — sab signals yahan

TIMING :
  Synchronous  : ek CLOCK sabke liye — simple, fast, fixed speed
  Asynchronous : HANDSHAKE (request → acknowledge) — alag-alag speed
                 ke devices smoothly judte hain, overhead thoda

Bus standard : PCI, PCIe, USB, SATA — protocol + physical connector

Yaad rakho: address bus ka width = addressable memory (32-bit → 4GB), data bus ka width = transfer per cycle. Dono ka farak exam mein classic confusion hai — address ek taraf, data dono taraf.

Numerical: 40-bit address bus → 2^40 = 1 TB addressable. Data bus 64-bit → 8 bytes per cycle. Ye dono calculations exam mein poochhi jaati hain — width × cycle rate = bandwidth (bytes/sec).

Bus arbitration aur control

Bus arbitration: ek time pe ek hi device bus lega — kaun le ye decide karna.
Daisy chain: priority chain mein pass hoti hai — simple, lekin top device hamesha jeet (starvation).
Centralized: ek arbiter chip decide karti hai — fair, single point.
Distributed: devices aapas mein decide karte hain — no single point, complex.
Bus master: jo directly transfer control chalaye (DMA controller ek bus master hai).

Arbitration flow (request/grant) :
1. Device ko transfer chahiye → Bus Request (BR)
2. Arbiter check → Bus Grant (BG) diya
3. Device bus leta hai → transfer
4. Ho gaya → bus chhod diya (HOLD released)

CPU generally default master hota hai;
DMA ke aane par CPU HOLD/HALT signal se bus chhod deta hai

Yaad rakho: Synchronous = clock-based (fast, rigid). Asynchronous = handshake (flexible, slow-thoda). Arbitration ke teen tarike — daisy chain, centralized, distributed — UGC-NET ka poochha hua sawaal hai.

DMA — CPU ke bina transfer

DMA (Direct Memory Access) : block data ko I/O ↔ memory
DIRECTLY transfer karta hai — CPU sirf setup karta hai

DMA steps :
1. Device/CPU → DMA ko request : kahan se, kahan tak, kitna
2. DMA bus maangta hai (bus request → grant)
3. DMA directly memory ↔ device transfer (CPU idle/thoda chalta)
4. Transfer complete → DMA CPU ko INTERRUPT deta hai

MODES :
  Cycle stealing  : ek-ek cycle chura ke, beech beech mein CPU ko
                   diya — CPU thoda slow hota hai, smooth
  Burst (block)   : poora block ek saath — tez, CPU thoda rukta
  Transparent     : sirf CPU ke idle cycles mein — CPU ko
                   bilkul affect nahi, par device ko wait

Interrupt vs DMA :
  Interrupt-driven : har word/byte pe CPU bulao (chhote transfers)
  DMA : ek setup + ek interrupt, beech ka CPU free (bade blocks)

DMA ka fayda simple hai: CPU ko byte-byte ka kaam nahi karna padta. Disk se 1MB data padhna ho toh interrupt mode mein CPU har byte pe rukta, DMA mein ek baar bola aur aage CPU apna kaam karta rehta.

Interview question: Q: "DMA ke baad CPU ko kaise pata chalta hai?" A: completion interrupt se. Q: "Cycle stealing kya hai?" — DMA cycle-che CPU ke hisse ke, taki CPU bilkul block na ho. Ye dono har interview round mein aate hain.

Exercise

Question: Address bus 32-bit hai toh maximum addressable memory kitni? (4 gb / 4 mb / 8 gb)

Question: DMA ka full form kya hai? (do words, space se)

Question: Data bus uni-directional hai ya bi-directional?

Common mistakes

Address aur data bus ka farak ulta bolna: Address bus = one-way (CPU se out), data bus = two-way (read+write). Width ka meaning bhi alag — addressable memory vs transfer size.
DMA ko interrupt samajhna: DMA direct transfer karta hai (CPU ke bina). Interrupt sirf start/end ke lagte hain — beech ka data CPU se nahi guzarta.
Arbitration ki zarurat na samajhna: Bus shared hai — agar do devices ek saath chala dein toh data kharab. Isliye arbitration zaroori hai (kaun kab bus lega).

Desi example: Traffic aur highway ka system

Bus ko highway samjho — lane ka width, signal, aur VIP gaadi (DMA):

Address bus : naya shehar bhejne ka PINCODE (ek taraf)
Data bus    : maal aata-jata hai (donon taraf)
Control bus : police ka signal (jaao/ruko)
Arbitration : signal wala — kaun kab guzre (priority)
DMA         : metro/rail — bina signal ruke maal pochhata hai
Cycle steal : beech mein chhota sa rasta de diya gaadi ko

Exam mapping (GATE / TCS / UGC)

GATE: bus width se memory size calculation (32-bit → 4GB).
GATE: DMA modes (cycle stealing vs burst) aur interrupt-driven comparison.
UGC-NET: bus arbitration techniques — daisy chain, centralized, distributed.
Trap: "Address bus is bidirectional" — galat, data bus bidirectional hai.

Lesson complete?

Buses aur DMA clear — ab Module 2 complete! Ab Module 3 — Instruction Pipelining — mein dekhenge CPU ek saath kitne instructions kaise chalata hai.