Lesson 14 — Intermediate

RISC vs CISC

Processor design ki sabse purani ladai — instructions rakho kam aur simple (RISC) ya rakho bahut aur complex (CISC)? Is lesson mein hum dono philosophies ki characteristics dekhenge, point-by-point compare karenge, aur dekhenge aaj ki duniya mein dono kahan khade hain.

⏱ 13 min• Intermediate• I/O Organization

RISC aur CISC kya hai

WHAT

CISC (Complex Instruction Set Computer) — bade complex instructions, har instruction ka kaam bahut (memory access + arithmetic ek saath). RISC (Reduced Instruction Set Computer) — chhote simple instructions, tez, pipeline-friendly, har instruction ek hi kaam.

WHEN

Processor design ke waqt decide hota hai — 70-80s mein CISC chala (memory mehngi thi, code chhota rakho). 80s ke baad RISC aaya (memory sasti, CPU tez karo).

WHERE

CISC → x86 laptops/desktops (Intel, AMD). RISC → phones (ARM), routers, embedded, supercomputers (RISC-V, MIPS, POWER). Tumhara phone RISC pe chalta hai.

Background samjho: CISC ka logic — memory mehngi thi, compiler ko chhota code do (complex instruction = kam instructions). RISC ka logic — memory ab sasti hai, CPU ko simple rakho taaki woh tez clock par pipeline chalaye.

CISC ke characteristics

CISC (Complex Instruction Set Computer) :
  - Instructions COMPLEX : ek instruction memory access +
    arithmetic dono kar leta hai
    Ex (x86): ADD [mem], reg  → padho + jodo + likho (poora kaam)
  - Instruction LENGTH variable (1 se 15+ bytes)
  - Addressing MODES zyada (10-15+ types)
  - Registers KAM (accumulator wala style bhi milta hai)
  - Memory ACCESS directly instructions kar sakti hain
    (sirf load/store nahi)
  - Execution MULTI-CYCLE : complexity ke chalte
  - Control unit : aksar MICROPROGRAMMED (flexibility chahiye)
  - Code SIZE chhota (dense instructions)
  - Pipelining MUSHKIL (har instruction alag time leti hai)
  - Examples : Intel x86, AMD64, VAX, Motorola 68000

Yaad rakho: CISC ka D mantra hai — Dense code, Diverse addressing, Deep microcode. Complex instruction set ka kharcha CPU ko chukana padta hai — isi liye aaj ke x86 andar hi RISC jaisi micro-ops chalate hain.

RISC ke characteristics

RISC (Reduced Instruction Set Computer) :
  - Instructions SIMPLE, chhoti — ek instruction EK hi kaam
  - LOAD/STORE architecture : sirf LOAD aur STORE memory access
    karte hain, baaki sab register-register (ALU ops)
    Ex: ADD R1, R2, R3  (memory bilkul nahi chua)
  - Instruction LENGTH FIXED (ex: 32-bit) — decode FAST
  - Addressing MODES kam (4-5 essential)
  - Registers ZYADA (32+) — compiler ko freedom
  - Execution mostly SINGLE-CYCLE (ek instruction, ek cycle)
  - Control unit : HARDWIRED (fast, simple instructions)
  - Hardwired + deep pipeline = high CLOCK speed
  - Compiler par bahut DEPENDENT (optimisation compiler chahiye)
  - Code SIZE bada (thoda) — lekin CPI bahut kam
  - Examples : ARM, MIPS, RISC-V, SPARC, POWER

Why simple = fast: simple instruction = jaldi decode = tez clock = deep pipeline possible.
Load/store ka faida: ALU instructions memory ke bina — memory slow hai, use kam karo.
More registers: beech ke results register mein rehte hain → memory traffic kam (cache misses kam).

Point-by-point comparison aur modern reality

Parameter        | CISC                    | RISC
-----------------+-------------------------+------------------------
Instruction set  | bada, complex           | chhota, simple
Instruction len  | variable                | fixed (32-bit)
Addressing modes | 10-15+                  | 4-5
Memory access    | instructions directly   | sirf LOAD/STORE
Registers        | kam                     | zyada (32+)
CPI              | zyada (2-15)            | kam (≈1)
Clock speed      | comparatively kam       | tez
Control unit     | microprogrammed         | hardwired
Pipeline         | mushkil                 | aasaan + deep
Compiler role    | limited                 | bahut important
Code density     | HIGH (chhota code)      | thoda bada
Examples         | x86, x64                | ARM, MIPS, RISC-V

Result pehle se hi clear hai : speed ke liye CPI × clock —
RISC ka formula behtar, aur aaj ARM servers/laptops mein x86
ko chhod raha hai (Apple M-series = RISC ARM!)

Modern reality: dono ka mix hai. x86 (CISC) internally instructions ko chhote RISC-like micro-ops mein todta hai (decode → µops → pipeline). ARM (RISC) mein bhi complex instructions badhi ja rahi hain. Matlab — philosophy mili hui hai, sirf face alag hai.

Interview answer: 4 line ka answer: "CISC = complex instructions, variable length, microcoded, memory ops direct. RISC = simple fixed instructions, load/store, hardwired, pipeline-friendly. Aaj x86 internally RISC jaisa chalta hai aur ARM dominance badh raha hai." — ye sun ke interviewer impress hoga.

Exercise

Question: RISC ka full form kya hai? (do words ya teen, space se — reduced instruction set computer)

Question: RISC mein memory access sirf kin instructions tak seemit hai? (load aur store / saari arithmetic / sirf add)

Question: CISC philosophy ka sabse famous commercial example processor kaunsa hai — x86 ya ARM?

Common mistakes

RISC ko chhota-capability samajhna: RISC ka matlab kam kaam nahi — instructions simple hain, par wohi sab karte hain. Complexity compiler aur pipeline mein shift hui hai.
Fixed vs variable length ulta bolna: RISC = fixed length (fast decode), CISC = variable (dense code). Ye dono taraf se poochha jaata hai.
Aaj bhi purani ladai samajhna: Modern x86 CISC face + RISC core (micro-ops), ARM bhi badh raha hai. Dono ka fayda aaj ek chip mein hai — interview mein ye nuance dikhao.

Desi example: Big restaurant vs fast food menu

Menu ka farak hi RISC-CISC ka farak hai:

CISC : bada restaurant, 200 dishes
  ek order mein sab kuch (customise + combo) — kitchen complex
  code chhota, par waiting variable
RISC : fast-food menu, 20 dishes
  sab fixed, tez ban jaate (assembly line pipeline)
  thoda zyada order karna padta hai, par average time kam
Apple M-series = RISC ARM → battery + speed dono

Exam mapping (GATE / TCS / Interviews)

UGC-NET/TCS: RISC vs CISC difference table — sabse common question.
GATE: load/store architecture aur CPI/clock comparison concept.
Interview: "ARM phone mein kyun?" — RISC power efficiency + speed.
Trap: "CISC uses hardwired control" — galat, CISC mein microprogrammed common hai.

Lesson complete?

RISC vs CISC clear — Module 3 ka core ho gaya. Ab last lesson — Top 50 COA Interview Questions — jo poore course ka revision hai.