Lesson 12 — Intermediate
Pipeline Hazards & Stalls
Pipeline chal rahi hai, lekin kabhi instruction ruk jaati hai — wo hazard hai. Is lesson mein hum dekhenge hazard ke teen type (structural, data, control), data hazards ka detailed example (RAW/WAR/WAW), unke solutions — forwarding, stalls, branch prediction — aur stall counting ka numerical kaise karte hain.
Hazard kya hai
WHAT
Pipeline hazard wo condition hai jismein agli instruction ko pehle wali complete hone se pehle rokna padta hai (stall), warna galat result aa jaayega. Jaise assembly line mein pehle station aage na badhe — peeche wale ko rukna padta hai.
WHEN
Jab instructions data ya resource par depend karti hain, ya jab branch flow badal de. Har real program mein hazards aate rehte hain.
WHERE
Instruction pipeline ke beech — EX se dependent instruction, memory port ka conflict, branch ke baad galat fetch — teeno jagah alag hazard.
Hazard ka matlab dependency ya conflict hai. Isliye solutions bhi wahi hain — conflict hatao (resource alag), dependency ka result jaldi do (forwarding), ya ruk jao (stall).
Teen type ke hazards
1) STRUCTURAL HAZARD : do instructions ko EK hi resource
chahiye ek hi cycle mein
Ex: single memory port — instruction fetch aur data access ek saath
Solution : separate instruction/data memory (Harvard)
multi-port memory, ya stage ko do alag cycle do
2) DATA HAZARD : instruction ko data chahiye jo abhi banna hai
Ex: ADD ke baad uska result wali instruction
Solution : forwarding, stalling, compiler scheduling
3) CONTROL HAZARD : branch/jump ne flow badla — pipeline ne
GALAT aage ke instructions fetch kar liye the
Ex: BEQ ke andar pehle hi 2 instructions ghus gayi
Solution : branch prediction, delayed branch, flush
Har GATE question in 3 mein se ek hota hai — type pehchano,
solution yaad aayega
Structural ka matlab resource ki kamti, data ka matlab dependency, control ka matlab flow change. Ek line mein type identify karna = aadha question solve.
Data hazards — RAW, WAR, WAW (example ke saath)
RAW — Read After Write (SABSE COMMON) :
ADD R1, R2, R3 ; R1 ko likh raha hai (result)
SUB R4, R1, R5 ; R1 ko PADH raha hai — result abhi bana nahi!
→ SUB ko roko ya result jaldi bhejo (forwarding)
WAR — Write After Read (anti-dependency) :
SUB R4, R1, R5 ; R1 padha
ADD R1, R2, R3 ; R1 ko dobara likhna — purana read ho jaye pehle
(in-order pipeline mein kam, out-of-order mein possible)
WAW — Write After Write (output dependency) :
ADD R1, R2, R3
SUB R1, R4, R5 ; dono R1 pe likhte hain — last wala jeete
FORWARDING (bypassing) :
EX ka result agle instruction ke EX input tak seedha wire se
bhejo — memory/WB tak ka wait khatam
Without forwarding : RAW par 2 stalls
With forwarding : EX-result → 0 extra stall
LOAD-USE hazard : data toh MEM mein aayega — 1 stall minimum
LOAD R1, [A]
ADD R2, R1, R3 ; MEM→EX bypass bhi ho toh 1 cycle chahiye
- RAW sabse common hai kyunki zyada tar programs mein sequence hota hai — banaya phir use kiya.
- Forwarding hardware se solve hota hai — compiler ko chedchad nahi karni padti.
- Load-use ek special case hai — jaldi karna possible nahi, ek stall toh chahiye (GATE mein poochha jaata hai).
- WAR/WAW out-of-order pipelines mein problem bante hain — simple in-order mein control logic sambhal leta hai.
Solutions — forwarding, prediction, flush
- Forwarding/Bypassing: result ko stage ke andar hi agle ko de do — sabse popular solution.
- Stalling: waqt do — bubble insert karo. Sahi par expensive (CPU khali baith raha hai).
- Compiler scheduling: instructions reorder karo taaki dependency door ho (delay slots bhar do).
- Branch prediction: guess karo branch jayegi ya nahi — predict sahi = koi penalty nahi.
- Delayed branch: branch ke baad wali slot hamesha chalti hai (RISC classic).
- Flush/Squash: galat predict ho gaya toh pipeline se ghusi instructions phenk do.
Control hazard ka penalty :
branch EX mein pata chalta hai → 1-2 instructions galat fetch
Penalty = 0 se 3+ cycles (prediction ke hisaab se)
Prediction strategies :
Always taken / Always not-taken : ~60-70% accuracy
1-bit / 2-bit saturating counter : loops mein bahut behtar
Dynamic + BTB (Branch Target Buffer) : modern CPUs yahi
Structural ka solution :
L1 split (L1I + L1D) = memory port conflict khatam
Multi-port register file = do reads + ek write ek saath
Exercise
Question: ADD ke baad uska result padhne par jo sabse common data hazard hota hai uska naam? (raw / war / waw)
Question: Branch instruction ki wajah se aane wale hazard ko kya kehte hain? (control hazard / structural hazard / data hazard)
Question: Full forwarding ke baad bhi LOAD-USE hazard mein minimum kitne stalls lagte hain? Sirf number daalo.
Common mistakes
- Load-use ko forwarding se zero bolna: Load ka data MEM stage mein aata hai — EX se pehle forward nahi ho sakta. Ek stall minimum chahiye, ye GATE ka favourite trap hai.
- Hazard aur stall ko same samajhna: Hazard = dependency/conflict ki situation, stall = usse bachne ka ek solution (rukna). Forwarding se hazard solve hota hai bina ruke.
- Structural vs data hazard confuse karna: Structural = resource ki kamti (memory/port). Data = data dependency. Agar option mein "same memory used" dikhe — structural hai.
Stall ka asli nazaara — station aage nahi badh raha toh peeche wali line ruk jaati hai:
Grill wala bole "paneer marinate hi nahi" (RAW hazard)
Solution A : marinate wala seedha de (FORWARDING)
Solution B : 1 min ruko (STALL — line khali)
Order badal diya beech mein (CONTROL hazard) → phenk do jo bana
Sabke liye alag grill (structural) → conflict khatam- GATE: stall counting (forwarding ke saath/without) — 2 marks ka regular question.
- GATE: hazard type identify karna (RAW vs structural vs control).
- TCS/Infosys: "RAW kya hai?" aur "forwarding kaise kaam karta hai" — verbal.
- Trap: "Forwarding eliminates all stalls" — galat, load-use ek stall chhodta hai.
Hazards clear — ab tum pipeline ke rukawatein aur unke ilaaj bata sakte ho. Agla lesson — I/O Organization & Interrupts — mein dekhenge CPU devices se kaise communicate karta hai.