Lesson 7 — Intermediate

Memory Hierarchy

CPU ko chahiye tez bhi, aur data chahiye bahut bada bhi — dono ek saath possible nahi. Isliye computers memory hierarchy banate hain. Is lesson mein hum dekhenge hierarchy ka order aur logic, SRAM aur DRAM ka farak, memory chips ka sizing numerical, aur interleaving kaise speed badhati hai.

⏱ 15 min• Intermediate• Control Unit

Memory hierarchy kyun chahiye

WHAT

Memory hierarchy speed, size aur cost ke balance ka naam hai — tez memory mehngi aur chhoti, sasti memory dheemi aur badi. Isliye unhe layers mein arrange kiya jaata hai: registers → cache → RAM → disk.

WHEN

Hamesha — har access pe CPU sabse upar wali layer check karta hai, aur wahan na mile toh neeche. Pura system isi principle par chalta hai.

WHERE

Har computer, phone aur server mein — registers CPU ke andar, cache uske paas, RAM board pe, disk andar. Poora stack isi hierarchy ka hai.

Problem ye thi: CPU 100× RAM se tez hai, aur agar CPU ko har cheez ke liye disk tak jaana pade toh rukta hi rehta. Hierarchy ka solution — chhoti-fast memory mein hot working set rakho, baaki bada data dheemi memory mein.

Hierarchy ka order aur economics

Speed (fast → slow) :
  Registers > Cache (L1>L2>L3) > Main Memory (RAM) > SSD > HDD > Tape

Size (chhota → bada) :
  Registers < Cache < RAM < SSD/HDD < Tape/Cloud

Cost per MB (mehnga → sasta) :
  Registers > Cache > RAM > SSD > HDD > Tape

Ek hi cheez dono taraf extreme hai — speed aur cost ka TRADE-OFF.
Hierarchy ka fayda : CPU ko lagta hai jaise sab kuch tez hai
(EFFECTIVE access time bahut kam aa jaata hai)

Registers: CPU ke andar, cycle mein milte hain, bytes mein size.
Cache: ns level, KB-MB, frequently used data rakhta hai.
RAM: working memory, GB, volatile.
SSD/HDD: permanent, TB, microsecond-millisecond.
Tape/Cloud: backup, huge, sabse dheema.

Yaad rakho: Hierarchy ka asli khel hai average case ko fast banaana — 90%+ accesses top layers mein mil jaate hain, isliye average speed cache wali ho jaati hai jabki capacity poori RAM+disk wali.

SRAM vs DRAM vs ROM

SRAM (Static RAM)                 DRAM (Dynamic RAM)
  6 transistors per bit              1 transistor + 1 capacitor
  Bina refresh ke data rhta          Refresh chalta rehta hai
  (bada circuit)                     (chhota, dense, sasta)
  FAST (cache mein)                  Slow-ish (main memory mein)
  Mehnga per MB                      Sasta per MB
  Use : L1/L2/L3 cache               Use : main memory (8GB stick)

ROM : non-volatile, read-only — BIOS/firmware
Flash : SSD wala — NAND based, rewriteable, non-volatile

DRAM variants : SDRAM, DDR, DDR4/DDR5 (double data rate)

Memory ka bada rule: volatility — RAM (SRAM/DRAM) volatile hain (power jaate hi gaya), ROM/Flash non-volatile. Aur DRAM ka refresh chalu rehna chahiye warna capacitor ka charge leak ho jaata hai — data gaya.

Interview question: Q: "Cache mein kaunsi RAM?" A: SRAM (fast, no refresh). Q: "Desktop RAM?" — DRAM. Reason: cost — poora memory SRAM banao toh 8GB ka kitna mehnga hoga, isliye hierarchy ka concept hi balance hai.

Memory sizing aur interleaving (numericals)

MEMORY CHIP SIZING :
  Capacity = 2^(address lines) × data lines
  1K × 8 chip → 10 address lines, 8 data lines (1KB per chip)

  Question : 16 KB memory chahiye, chips = 1K × 8
  Chips = 16K / 1K = 16 chips (data width same hai, depth judi)

  Address lines kitne chahiye 4KB ke liye? → log2(4K) = 12 lines

INTERLEAVING :
  Total memory modules mein distribute karo addresses
  k-way interleaving : address ke LOW-order bits module select
  Example 4-way : addr[1:0] = module number

  Low-order → paas wale words alag modules → PARALLEL fetch (fast)
  High-order → ek module mein burst — sequential kaam ke liye

Sizing numerical ka rule simple hai: depth judti hai (address lines), width match rehta hai (data lines). Aur interleaving ka logic — address ke lower bits module chunate hain, taaki consecutive accesses alag modules pe ho jaayein aur memory parallel chale.

GATE trap: Interleaving mein module number LOWER order bits se nikalte hain (low-order interleaving). Agar option mein "higher order bits" de — wo high-order interleaving hai jo burst transfer ke liye, speed ke liye nahi.

Exercise

Question: Hierarchy mein cache ke turant neeche kaun aata hai — RAM ya registers?

Question: 1K × 8 memory chip ke kitne address lines honge? Sirf number daalo.

Question: Cache memory mein kaunsi RAM use hoti hai — SRAM ya DRAM?

Common mistakes

SRAM aur DRAM ka use ulta bolna: SRAM = cache (fast, mehnga, no refresh), DRAM = main memory (dense, sasta, refresh chahiye). Exam mein use poochha jaata hai.
Speed aur size ka order ulta ratna: Speed: registers > cache > RAM > disk. Size: ulta. Do alag orders hain — mix mat karna.
Chip sizing mein data lines jod dena: Chips ko series mein jodne se depth (locations) badhti hai, parallel mein width. Data width match honi chahiye ya chips parallel karo.

Desi example: Mess ki serving system

Mess mein serving ka hierarchy hai — jaldi wali cheez paas, bulk neeche. Yahi memory hierarchy hai:

Table pe roti (register)  : turant, bahut thoda
Counter (cache)           : fast, limited variety
Kitchen (RAM)             : thoda wait, zyada
Godown (disk)             : delivery time, bahut bada
Cost/peed ka balance = hierarchy ka asli kaam

Exam mapping (GATE / TCS / UGC)

GATE: chip sizing numerical (address lines, number of chips).
GATE: interleaving mein module select ka bit order.
TCS NQT: SRAM vs DRAM — classic comparison question.
Trap: "DRAM needs no refresh" — galat, DRAM ko regular refresh chahiye.

Lesson complete?

Hierarchy ka order clear. Agla lesson — Cache Memory — mein detail mein dekhenge mapping techniques, hit-ratio aur AMAT ka numerical.